library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity icy_delay is
    port(clk, rst:in std_logic;
         pul:out std_logic);
end icy_delay;

architecture behav of icy_delay is
signal cnt:std_logic_vector(23 to 0);
begin
    process(clk, rst)
    begin
        if(rst = '0') then
            cnt <= "000000000000000000000000";
        elsif(clk'event and clk = '1') then
            if(cnt="100110001001011001111111") then -- interval: 20ms
                cnt <= "100110001001011001111111"; pul <= '0';
            else cnt <= cnt + '1'; pul <= '1';
            end if;
        end if;
    end process;
end behav;